The present invention relates to a method of manufacturing a semiconductor integrated circuit device, an optical mask therefor, its manufacturing method, and mask blanks; and, more particularly, the invention relates to a technique which can be effectively applied to the exposure technique used in the process of manufacturing a semiconductor integrated circuit device.
In the manufacture of a semiconductor integrated circuit device, a lithography technique is used as a method of transferring micro patterns onto semiconductor wafers. In the lithography technique, a projection exposure system is mainly used; wherein, the pattern of a photo mask provided on the projection aligner is transferred onto a semiconductor wafer to thereby form a device pattern.
The ordinary photo mask examined by the present inventor is made by processing a light screening material such as chrominum (Cr) or the like formed on a transparent quartz substrate. In other words, the photo mask is constituted in such a manner that a light screening film comprised of chromium or the like is formed in a desired shape on the quartz substrate. The processing of the light screening film is carried out, for example, in the following manner. After an electron-beam-sensitive resist is applied onto the light screening film, a desired pattern is written on the electron-beam-sensitive resist by an electron beam lithography system. Subsequently, after the resistor pattern of a desired shape is formed by development the light screening film is processed by dry etching or wet etching by the use of the thus obtained resist pattern as a mask. After this, the resist is removed, cleaning or the like is carried out, and thus, a light shielding pattern of a desired shape is formed on the transparent quartz substrate.
Further, recently, various mask structures have been proposed for the purpose of enhancing the resolution of the lithography. For example, in Japanese Patent Laid-Open No. 136854/1992, there is disclosed a mask structure constituted in such a manner that, as a means for enhancing the resolution of a single transparent pattern, the portion surrounding the single transparent pattern is made semitransparent, in other words, the light screening portion of the photo mask is made semitransparent; and, thus, the phase of the slight amount of light passing through this semitransparent portion and the phase of the light passing through the transparent pattern are inverted with respect to each other. In other words, light that is below the sensitivity of the photo resist for transferring the pattern is allowed to pass through the semitransparent film, and the phase of this light and the phase of the light which has passed through the transparent pattern are inverted with respect to each other. The light which has passed through the semitransparent film is inverted in phase with respect to the light which has passed through the transparent pattern, which is the major pattern, so that its phase is inverted in the boundary portion of the patterns, and thus, the light intensity in the boundary portion approaches 0. As a result, the ratio between the intensity of the light which has passed the transparent pattern and the intensity of the light in the pattern boundary portion becomes large; and thus, a light intensity distribution with a contrast higher than in the case of the techniques using no semitransparent film is obtained. This is called a halftone type phase shift mask. In the manufacturing process of the halftone type phase shift mask, the light screening film of the above-mentioned ordinary photo mask is altered to a halftone phase shift film, so that the halftone type phase shift mask is manufactured by approximately the same process as the above-mentioned ordinary photo mask manufacturing process.
Further, for example in Japanese Patent Laid-Open No. 289307/1993, there is disclosed a method of forming a light screening film by the use of a resist film for the purpose of simplifying the photo mask manufacturing process and enhancing the precision. This method utilizes the properties of an ordinary electron-beam-sensitive or an ordinary light-sensitive resist that screens the vacuum ultraviolet rays with a wavelength below about 200 nm. According to this method, the step of etching the light screening film and the step of removing the resist are disused; and thus, the reduction in cost of the photo masks, the enhancement in dimensional accuracy thereof, and the reduction of defects thereof become possible.
Further, in Japanese Patent Laid-Open No. 181257/1993 for example, there is disclosed a so-called halftone mask constituted in such a manner that, on a substrate which is transparent with respect to the exposure light, a phase shift film comprising a semitransparent material which absorbs the exposure light is provided. In case of the technique disclosed in this Japanese Patent Laid-Open No. 181257/1993, the mask vacuum-holding surface is the mask substrate surface, so that exposure is executed with the mask surface directed to the exposure light source. In this case, the mechanical strength of the phase shift film comprising a semi-transparent material is high even at the periphery of the mask, and there is no problem with respect to mask absorption and the like. Further, as for the mask alignment, the mask has light screening properties, and thus, there seems to be no problem.
Further, in Japanese Patent Laid-Open No. 15830/1997 for example, there is disclosed a technique according to which, after a light shielding pattern is formed on a mask substrate, a phase shift film is formed to a film thickness greater than the film thickness corresponding to the target phase difference, and a desired portion provided with the phase difference is etched by an amount corresponding to the target phase difference.
However, in case of the above-mentioned technique, according to which the light shielding pattern on the photo mask is formed by a resist film, there are not disclosed the problematic point encountered when the photo mask is actually used in the process of manufacturing a semiconductor integrated device, the problematic point encountered in the actual photo mask manufacture, and the measures to counter these problematic points; and, the present inventor has found that the above-mentioned technique has the following problems.
More specifically, it is difficult to detect predetermined patterns, such as, e.g., an alignment mark, a pattern measuring mark or a product decision mark on the photo mask, which are used for the detection of various kinds of information. For example, in the case of a photo mask defect inspection system, an aligner and the like, which are used at present, a halogen lamp or the like is mainly used for the alignment of the photo mask. Accordingly, in case the photo mask is mounted on a defect inspection system or an aligner, if the detection mark on the photo mask is formed by a resist film pattern, then no high contrast can be obtained, since the resist mask is high in light transmissivity; and thus, the detection of the pattern is difficult. Due to this, it becomes difficult to align the photo mask with the defect inspection system or the aligner, and thus, there arises the problem that no good inspection or exposure can be made.
Further, when the photo mask is mounted onto the defect inspection system or the aligner, foreign matter is produced. In the case of the above-mentioned technique, when the photo mask is mounted onto the defect inspection system or the aligner, the resist film of the photo mask comes into direct contact with a photo mask fixing member (such as, e.g., a vacuum fixing member) of the defect inspection system or the aligner, so that, upon the breakage or peeling-off of the resist film, foreign matter is produced. This foreign matter tends to attach to the surface of, for example, the lens of the inspection system or the aligner, to contaminate the inside of the chamber or to attach to the surface of the semiconductor wafer, as a result of which, a deterioration of the inspection accuracy or the transfer accuracy of the pattern is brought about, and defects, such as short-circuit or open-circuit defects of the pattern are caused. Thus, the reliability and manufacturing yield of the semiconductor integrated circuit devices fall, this being another problem.
Thus, it is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit device using a photo mask constituted in such a manner that a resist film is made to function as a light screening film, wherein the information detecting ability of the above-mentioned photo mask can be enhanced.
Further, another object of the invention is to provide a method of manufacturing a semiconductor integrated circuit device using a photo mask constituted in such a manner that the resist mask is made to function as a light screening film, wherein the accuracy in the alignment of the photo mask with the inspection equipment or the exposure device can be enhanced.
Still another object of the invention is to provide a method of manufacturing a semiconductor integrated circuit device using a photo mask constituted in such a manner that a resist film is made to function as a light screening film, wherein the inspection accuracy of the photo mask inspection equipment can be enhanced.
Still another object of the invention is to provide a method of manufacturing a semiconductor integrated circuit device using a photo mask constituted in such a manner that a resist mask is made to function as a light screening film, wherein the accuracy in the pattern transfer of the aligner can be enhanced.
Further, still another object of the invention is to provide a semiconductor integrated circuit device using a photo mask constituted in such a manner that a resist film is made to function as a light screening film, wherein the occurrence of foreign matter can be suppressed or prevented.
Further, still another object of the invention is to provide a semiconductor integrated circuit device using a photo mask constituted in such a manner that a resist film is made function as a light screening film, wherein the reliability and manufacturing yield of semiconductor integrated circuit devices can be enhanced.
The above-mentioned and other objects and novel features of the present invention will be apparent from the description in the specification and the accompanying drawings.
Outlines of the representative aspects of the inventive features disclosed in the present application will be briefly described below.
According to the present invention, when an optical mask is mounted on a predetermined apparatus, such as a inspection equipment or an aligner, a light shielding pattern comprising a resist film on the mask substrate of the optical mask is disposed on the major surface of the mask substrate in such a manner that the light shielding pattern and the fitting portion of the predetermined apparatus is not contacted.
Further, according to the invention, when the optical mask is mounted onto the predetermined apparatus, a predetermined treatment is carried out on the major surface of the mask substrate of the optical mask in the state in which the fitting portion of the predetermined apparatus is contacted with a region in which the light shielding pattern comprising the resist film does not exist.
Further, according to the invention, a light shielding pattern comprising a resist film is disposed in an integrated circuit pattern region of a first mask substrate; in the outer periphery of the above-mentioned integrated circuit pattern region, a light screening metal region made of a metal is disposed; and an opening is provided in the light screening metal region, and a optical mask is used which is constituted in such a manner that a mask pattern for detecting the information of the optical mask is formed.
Further, according to the invention, a light shielding pattern comprising a resist film is disposed in an integrated circuit pattern region of a first major surface of a mask substrate; in the outer periphery of the integrated circuit pattern region, a light screening metal region comprising a metal is disposed; and further, when an optical mask is mounted onto an aligner, with the optical mask being constituted in such a manner that an opening is provided in the light screening metal region, and a mark pattern for detecting the information of the optical mask is formed, exposure light is irradiated from a second major surface side of the mask substrate, in the state in which the fitting portion of the aligner is in contact with a region in which the light shielding pattern comprising a resist film does not exist; and exposure light which has transmitted through the optical mask is projected by reduction exposure onto the semiconductor wafer, whereby the integrated circuit pattern is transferred onto the semiconductor wafer.
Further, according to the invention, a light shielding pattern comprising a resist film is disposed on an integrated circuit pattern region of a first major surface of a mask substrate; in the outer periphery of the integrated circuit pattern region, a light screening metal region made of a metal is disposed; an opening is provided in the light screening metal region, and a mark pattern is provided for detecting the information of the optical mask; and further, there is used an optical mask constituted in such a manner that a pellicle, which is fixed in a state in which the base portion of the pellicle is contacted with the light screening metal region or the mask substrate, is disposed on the first major surface side of the mask.
Further, according to the invention, when the optical mask is mounted on a predetermined apparatus, a predetermined treatment is carried out, on the major surface of the mask substrate of the optical mask, in a state in which the fitting portion of the predetermined apparatus is in contact with a region in which a halftone pattern comprising a resist film does not exist.
Further, according to the invention, a light shielding pattern comprising a resist film is disposed in an integrated circuit pattern region on a first major surface of the mask substrate; in the outer periphery of the integrated circuit pattern region, a light screening metal region comprising a metal is disposed; an opening is provided in the light screening metal region, and a mark pattern is provided for detecting the information of the optical mask; and further, on the first major surface of the mask substrate, there is provided a phase shift film for causing the exposure light which has transmitted through the optical mask to produce a phase difference.
Further, outlines of other aspects of the inventive features disclosed in the present application will be briefly described below.
1. A method of manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of irradiating far ultraviolet or vacuum ultraviolet exposure light from a second major surface side of a mask substrate, the mask substrate having on a first major surface thereof a light shielding pattern which is an integrated circuit pattern on a mask and comprises a photo resist pattern; and
(b) the step of reduction-projecting, by a projection optical system, said exposure light which has transmitted through said mask substrate, whereby the integrated circuit pattern is imaged on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer and thus transferred.
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the wavelength of the exposure light is at least 100 nm less than 250 nm.
3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the wavelength of said exposure light is at least 100 nm but less than 200 nm.
4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein, in the peripheral portion of the first major surface of the mask substrate, a light screening metal region is provided.
5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein, on the first major surface of said mask substrate, a pellicle is provided so as to cover said integrated circuit pattern, said pellicle being contact-fixed on said light screening metal region.
6. A method of manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of irradiating far ultraviolet or vacuum ultraviolet exposure light from a first major surface or a second major surface side of the mask substrate in the state in which the peripheral region of the mask substrate is held on a mask holding mechanism, the mask substrate having on the first major surface thereof a light shielding pattern which is an integrated circuit pattern on a mask and comprises a photo resist pattern, the resist pattern being not provided on the peripheral region; and
(b) the step of reduction-projecting, by a projection optical system, the exposure light which has transmitted through said mask substrate, whereby the integrated circuit pattern is imaged on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer and thus transferred.
7. The method of manufacturing a semiconductor integrated circuit according to claim 6, wherein the wavelength of the exposure light is at least 100 nm but less than 250 nm.
8. The method of manufacturing a semiconductor integrated circuit according to claim 7, wherein, wherein the wavelength of the exposure light is at least 100 nm but less than 200 nm.
9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein, in the peripheral portion of the first major surface of the mask substrate, a light screening metal region is provided.
10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein, on the first major surface of the mask substrate, a pellicle is provided so as to cover said integrated circuit pattern, said pellicle being contact-fixed on said light screening metal region.
11. A method of manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of irradiating far ultraviolet or vacuum ultraviolet exposure light from a first major surface or second major surface side of a mask substrate, the mask substrate having, in an integrated circuit pattern region of the first major surface thereof, a light shielding pattern which is an integrated circuit pattern on a mask and comprises a photo resist pattern and having a light screening metal region provided in the peripheral region of the first major surface; and
(b) the step of reduction-projecting, by a projection optical system, said exposure light which has transmitted through the mask substrate, whereby, on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, the integrated circuit pattern is imaged and thus transferred.
12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the wavelength of the exposure light is at least 100 nm but less than 250 nm.
13. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the wavelength of the exposure light is at least 100 nm but less than 200 nm.
14. The method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein, on the first major surface of the mask substrate, a pellicle is provided so as to cover the integrated circuit pattern, the pellicle being contact-fixed on the light screening metal region.
15. A method of manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of irradiating far ultraviolet or vacuum ultraviolet exposure light from a first major surface or a second major surface side of a mask substrate, the mask substrate having, in an integrated circuit pattern region of the first major surface thereof, a light shielding pattern which is an integrated circuit pattern on a mask and comprises a photo resist pattern, wherein a pellicle is contact-fixed in that part of the peripheral portion of the integrated circuitpattern region in which the photo resist pattern is not formed so as cover said integrated circuit pattern; and
(b) the step of reduction-projecting, by a projection optical system, said exposure light which has transmitted through the mask substrate, whereby, on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, the integrated circuit pattern is imaged and thus transferred.
16. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the wavelength of the exposure light is at least 100 nm but less than 250 nm.
17. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the wavelength of the exposure light is at least 100 nm but less than 200 nm.
18. The method of manufacturing a semiconductor integrated circuit device according to claim 17, wherein, in the peripheral portion of the first major surface of the mask substrate, a light screening metal region is provided.
19. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein, on the first major surface of said mask substrate, the pellicle is contact-fixed on said light screening metal region.
20. A method of manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of irradiating far ultraviolet or vacuum ultraviolet exposure light from a first major surface side or a second major surface side of a mask substrate, the mask substrate having, on the first major surface thereof, a halftone light shielding pattern comprising a photo resist pattern which constitutes an integrated circuit pattern on a mask; and
(b) the step of reduction-projecting, by a projection optical system, the exposure light which has transmitted through the mask substrate, whereby, on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, the integrated circuit pattern is imaged and thus transferred.
21. The method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein the wavelength of the exposure light is at least 100 nm but less than 250 nm.
22. The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein the wavelength of the exposure light is at least 100 nm but less than 200 nm.
23. The method of manufacturing a semiconductor integrated circuit device according to claim 22, wherein, in the peripheral portion of the first major surface of the mask substrate, a light screening metal region is provided.
24. The method of manufacturing a semiconductor integrated circuit device according to claim 23, wherein, on the first major surface of the mask substrate, a pellicle is provided so as to cover said integrated circuit pattern, said pellicle being contact-fixed on the light screening region.
25. A method of manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of irradiating far ultraviolet or vacuum ultraviolet exposure light from a first major surface side or a second major surface side of a mask substrate, which has, on the first major surface thereof, a light shielding pattern which is an integrated circuit pattern on a Lebenson type phase shift mask and comprises a photo resist pattern; and
(b) the step of reduction-projecting, by a projection optical system, the exposure light which has transmitted through said mask substrate, whereby, on a first major surface of a semiconductor integrated circuit wafer, said integrated circuit pattern is imaged and thus transferred.
26. The method of manufacturing a semiconductor integrated circuit device according to claim 25, wherein the wavelength of the exposure light is at least 100 nm but less than 250 nm.
27. The method of manufacturing a semiconductor integrated circuit device according to claim 26, wherein, wherein the wavelength of the exposure light is at least 100 nm but less than 200 nm.
28. The method of manufacturing a semiconductor integrated circuit device according to claim 27, wherein, in the peripheral portion of the first major surface, a light screening metal region is provided.
29. The method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein, on the first major surface of the mask substrate, a pellicle is provided so as to cover said integrated circuit pattern, the pellicle being contact-fixed on the light screening metal region.
30. A method of manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of irradiating far ultraviolet or vacuum ultraviolet exposure light from a first major surface or a second major surface side of a mask substrate, the mask substrate having, in an integrated circuit pattern region of the first major surface thereof, a light shielding pattern which is an integrated circuit pattern on a mask and comprises a photo resist pattern, wherein a pellicle is contact-fixed in the peripheral portion of the integrated circuit pattern of said first major surface so as to cover said integrated circuit pattern; and
(b) the step of reduction-projecting, by a projection optical system, the exposure light which has transmitted through the mask substrate, whereby, on a photo resist film formed on a first major surface of a semiconductor integrated circuit, the integrated circuit pattern is imaged and thus transferred.
31. The method of manufacturing a semiconductor integrated circuit device according to claim 30, wherein the wavelength of the exposure light is at least 100 nm but less than 250 nm.
32. The method of manufacturing a semiconductor integrated Circuit device according to claim 31, wherein the wavelength of the exposure light is at least 100 nm but less than 200 nm.
33. The method of manufacturing a semiconductor integrated circuit device according to claim 32, wherein, in the peripheral portion of the first major surface of the mask substrate, a light screening metal region is provided.
34. The method of manufacturing a semiconductor integrated circuit device according to claim 33, wherein, on the first major surface of the mask substrate, a pellicle is provided so as to cover the integrated circuit pattern, the pellicle being contact-fixed on the light screening metal region.
35. A method of manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of irradiating far ultraviolet or vacuum ultraviolet exposure light from a first major surface or a second major surface side of a mask substrate, the mask substrate having, in an integrated circuit pattern region of said first major surface thereof, a light shielding pattern which is an integrated circuit pattern on a mask and comprises a photo resist pattern, wherein a protective film is formed on the photo resist pattern so as to cover said integrated circuit pattern region of the first major surface; and
(b) the step of reduction-projecting, by a projection optical system, the exposure light which has transmitted through the mask substrate, whereby, on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, the integrated circuit pattern is imaged and thus transferred.
36. The method of manufacturing a semiconductor integrated circuit device according to claim 35, wherein the wavelength of the exposure light is at least 100 nm but less than 250 nm.
37. The method of manufacturing a semiconductor integrated circuit device according to claim 36, wherein the wavelength of the exposure light is at least 100 nm but less than 200 nm.
38. A method of manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of irradiating far ultraviolet or vacuum ultraviolet exposure light from a first major surface or a second major surface side of a mask substrate, the mask substrate having, in an integrated circuit pattern region of the first major surface thereof, a light shielding pattern which is an integrated circuit pattern on a mask and comprises a photo resist pattern, wherein a conductive ground film is formed beneath said photo resist pattern on said first major surface; and
(b) the step of reduction-projecting, by a projection optical system, said exposure light which has transmitted through the mask, whereby, on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, said integrated circuit pattern is imaged and thus transferred.
39. The method of manufacturing a semiconductor integrated circuit device according to claim 38, wherein the wavelength of the exposure light is at least 100 nm but less than 250 nm.
40. The method of manufacturing a semiconductor integrated circuit device according to claim 39, wherein the wavelength of the exposure light is at least 100 run but less than 200 run.
41. Mask blanks for the reduction projection exposure of vacuum ultraviolet rays, comprising:
(a) a mask substrate which has first and second major surfaces and is transparent with respect to far ultraviolet rays or vacuum ultraviolet rays with a wavelength of at least 100 nm but less than 250 nm;
(b) a region coated with a light screening metal film which region is formed on the first major surface of the mask substrate; and
(c) an opening region provided in the portion corresponding to an integrated circuit pattern region in the central portion of the region coated with a light screening metal film.
42. The method of manufacturing a semiconductor integrated circuit device according to claim 41, wherein the wavelength of the exposure light is at least 100 nm but less than 200 nm.
43. A method of manufacturing an optical mask for performing the reduction projection exposure of a semiconductor integrated circuit device, wherein far ultraviolet rays or vacuum ultraviolet rays are used as the exposure light, comprising:
(a) the step of placing a mask substrate on a processed mask holding portion of a mask writer;
(b) the step of detecting a position detecting pattern provided in the peripheral portion of a first major surface of the mask substrate; and
(c) the step of calibrating an integrated circuit pattern to the position where it is to be written, on the basis of the result of the above-mentioned detection, whereby the integrated circuit pattern is written on an integrated circuit pattern region on said first major surface.
44. The method of manufacturing a semiconductor integrated circuit device according to claim 43, wherein the wavelength of the exposure light is at least 100 nm but less than 250 nm.
45. The method of manufacturing a semiconductor integrated circuit device according to claim 44, wherein the wavelength of the exposure light is at least 100 nm but less than 200 nm.
46. An optical mask comprising:
(a) a mask substrate which has first and second major surfaces and is transparent with respect to far ultraviolet or vacuum ultraviolet rays;
(b) an integrated circuit pattern region of the first major surface of the mask substrate;
(c) an integrated circuit pattern on the mask substrate, the integrated circuit pattern being formed of a light shielding pattern in said integrated circuit pattern region of the mask substrate and being imaged on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, by reduction-projecting, by means of a projection optical system, the exposure light which has transmitted through the mask substrate, the integrated circuit pattern being thus transferred; and
(d) a light screening metal region provided in the peripheral region of the first major surface of the mask substrate.
47. An optical mask comprising:
(a) a mask substrate which has first and second major surfaces and is transparent with respect to far ultraviolet or vacuum ultraviolet rays;
(b) an integrated circuit pattern region of the first major surface of the mask substrate; and
(c) an integrated circuit pattern on the mask substrate, the integrated circuit pattern being formed, in the integrated circuit pattern region of the mask substrate, of a halftone light shielding pattern which comprises a photo resist pattern, the integrated circuit pattern being imaged on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, by reduction-protecting, by means of a projection optical system, the exposure light which has transmitted through the mask substrate, the integrated circuit pattern being thus transferred.
48. An optical mask comprising:
(a) a mask substrate which has first and second major surfaces and is transparent with respect to far ultraviolet or vacuum ultraviolet rays;
(b) a Lebenson type phase shift means formed on said first major surface or second major surface;
(c) an integrated circuit pattern region of the first major surface of the mask substrate; and
(d) an integrated circuit pattern on a mask substrate, the integrated circuit pattern being formed, in said integrated circuit pattern region of the mask substrate, of a light shielding pattern which comprises a photo resist pattern, the integrated circuit pattern being imaged on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, by reduction-projecting, by means of a projection optical system, the exposure light which has transmitted through the mask substrate, the integrated circuit pattern being thus transferred.
49. An optical mask comprising:
(a) a mask substrate which has first and second major surfaces and is transparent with respect to far ultraviolet rays or vacuum ultraviolet rays;
(b) an integrated circuit pattern region of the first major surface of the mask substrate;
(c) an integrated circuit pattern on the mask substrate, the integrated circuit pattern being formed, in said integrated circuit pattern region of the mask substrate, of a halftone light shielding pattern which comprises a photo resist pattern, the integrated circuit pattern being imaged on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, by reduction-projecting, by means of a projection optical system, the exposure light which has transmitted through the mask substrate, the integrated circuit pattern being thus transferred; and
(d) a protective film covering the integrated circuit pattern region and the light shielding pattern.
Further, outlines of still others of the inventions disclosed in the present application will be briefly described below.
50. The present invention comprises
(a) the step of depositing a transparent conductive film on a first major surface of a mask substrate,
(b) the step of depositing a resist film on the transparent conductive film,
(c) the step of writing a predetermined integrated circuit pattern on the resist film in the state in which the transparent conductive film is grounded,
(d) the step of performing a developing treatment after the step (c), whereby a light shielding pattern constituted of the transparent conductive film and the resist film is formed on the first major surface of the mask substrate,
(e) the step of holding the optical mask, which has been fabricated by, the foregoing steps (a) to (d), in the state in which the light shielding pattern constituted of the conductive film and the resist film is not contacted with the mounting portion of an aligner, and then, irradiating far ultraviolet rays or vacuum ultraviolet rays from a second major surface side of the optical mask, and
(f) the step of reduction-projecting by means of a projection optical system the exposure light which has transmitted through the mask substrate, whereby, on a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, the integrated circuit pattern is transferred.
51. The invention comprises
(a) the step of depositing a resist film on a first major surface of a mask substrate,
(b) the step of depositing a water-soluble conductive film on the resist film,
(c) the step of writing a predetermined integrated circuit pattern on the resist film in the state in which the water-soluble conductive film is grounded,
(d) the step of removing the water-soluble conductive film by performing a developing treatment after the step (c), and forming a light shielding pattern, which comprises a resist film, on the first major surface of the mask substrate,
(e) the step of holding the optical mask, which has been fabricated through the foregoing steps (a) to (d), in the state in which the light shielding pattern thereof is not contacted with the mounting portion of an aligner, and then, irradiating far ultraviolet rays or vacuum ultraviolet rays from a second major surface side of the optical mask, and
(f) the step of reduction-projecting by means of a projection optical system the exposure light which has transmitted through the mask substrate, whereby, onto a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, the integrated circuit pattern is transferred.
52. The invention comprises
(a) the step of depositing a light screening film, which comprises a metal, on the whole of a first major surface of a mask substrate,
(b) the step of patterning the light screening film to form a common light shielding pattern on the first major surface of the mask substrate,
(c) the step of depositing a resist film on the whole of the first major surface of the mask substrate after the foregoing step (b), and (d) the step of patterning the resist film, whereby a light screening pattern for transferring an integrated circuit-pattern onto an integrating circuit pattern region is formed on the first major surface of the mask substrate.
53. The invention comprises
(a) the step of depositing a resist film on a first major surface of a mask substrate and, thereafter, patterning the resist film, whereby a light shielding pattern for forming an integrated circuit pattern is formed,
(b) the step of depositing a phase shift film on the first major surface of the mask substrate after the foregoing step (a),
(c) the step of digging a groove in the phase shift film so as to produce a phase difference between the light rays which have transmitted through the mask substrate,
(d) the step of mounting, on the mounting portion of an aligner, the optical mask fabricated through the foregoing steps (a) to (c), and then, irradiating far ultraviolet rays or vacuum ultraviolet rays from a second major surface side of the optical mask, and
(e) the step of reduction-projecting by means of a projection optical system the exposure light which has transmitted through the mask substrate, whereby, onto a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, the integrated circuit pattern is transferred.
54. The invention comprises
(a) the step of depositing a resist film on a first major surface of a mask substrate, and then, pattering this resist film to form a halftone pattern, which is a pattern for forming an-integrated circuit pattern and has the function of causing a phase difference between the transmitted light rays and lowering the intensity of the transmitted light rays than that of the light rays which have transmitted through the mask substrate,
(b) the step of mounting on the mounting portion of an aligner the optical mask fabricated through the foregoing step (a), and then, irradiating far ultraviolet rays or vacuum ultraviolet rays from a second major surface side of the optical mask, and
(c) the step of reduction-projecting by means of a projection optical system the exposure light which has transmitted through the mask substrate, whereby, onto a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer.
55. The invention comprises
(a) the step of depositing a resist film on a first major surface of a mask substrate, and then, patterning this resist film to form a halftone pattern which is pattern for forming an integrated circuit pattern and has the function of causing a phase difference between the transmitted light rays and lowering the intensity of the transmitted light rays than that of the light rays which have transmitted through the mask substrate,
(b) the step of using the halftone pattern as an etching mask and digging grooves in the mask substrate exposed from therefrom, whereby the phase difference of the transmitted light rays is adjusted,
(c) the step of mounting on the mounting portion of an aligner the optical mask fabricated through the foregoing steps (a) and (b), and then, irradiating far ultraviolet rays or vacuum ultraviolet rays from a second major surface side of the optical mask, and
(d) the step of reduction-projecting by means of a projection optical system the exposure light which has transmitted through the mask substrate, whereby, onto a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, the integrated circuit pattern is transferred.
56. The invention comprises
(a) the step of depositing, on a first major surface of a mask substrate, a phase adjusting film for adjusting the phase of the transmitted light,
(b) the step of depositing a resist film on the phase adjusting film, and then, patterning this resist film to form a halftone pattern, which is a pattern for forming an integrated circuit pattern and has the function of causing a phase difference between the transmitted light rays and lowering the intensity of the transmitted light than that of the light rays which have transmitted through the mask substrate,
(c) the step of using the halftone pattern as an etching mask and shaving off the phase adjusting film, which is exposed from the halftone pattern, wholly or by an amount corresponding to a predetermined thickness, whereby the phase difference of the transmitted light rays is adjusted,
(d) the step of mounting on the mounting portion of an aligner the optical mask fabricated through the foregoing steps (a) to (c), and then, irradiating far ultraviolet rays or vacuum ultraviolet rays from a second major surface side of the optical mask, and
(e) the step of reduction-projecting by means of a projection optical system the exposure light which has transmitted through the mask substrate, whereby, onto a photo resist film formed on a first major surface of a semiconductor integrated circuit wafer, the integrated circuit pattern is transferred.
57. The invention is constituted in such a manner that, in the preceding Item 54, 55 or 56, a light screening metal region is provided in the peripheral portion of the first major surface of the mask substrate.
58. The invention is constituted in such a manner that, in any one of the foregoing Items 50, 51 and 53 to 57, the wavelength of the exposure light is at least 100 nm but less than 250 nm.
59. The invention is constituted in such a manner that, in any one of the foregoing Items 50, 51 and 53 to 57, the wavelength of the exposure light is at least 100 nm but less than 200 nm.